Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of a constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-gm differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 μA with a supply voltage of 1.65 V in a standard CMOS 0.18 μm digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.